Rent’s Rule Coincidence or the Result of the Design Process?

The design process for VLSI systems requires several iterations of the physical design cycle. After a partitioning of the circuit and a floorplanning step, the circuit components are placed. The wires between the components are then routed taking the placement into account. A bad placement cannot be solved by a good routing. Therefore, the information obtained during routing generally leads to a new placement step to improve the placement results. A new routing is then performed and so on. In order to fasten the iteration process and to improve the placement and routing results, it is mandatory to efficiently use estimates of area, wire length, etc. Three kinds of estimates are used: a priori, on line, and a posteriori estimates [1, 2]. The first kind estimates circuit parameters before any of the layout steps (floorplanning, placement, or routing) is performed. On line estimates are obtained during the layout process and are based on the information that results from the layout process itself. A posteriori estimates are obtained after a complete layout step and present the layout results. A priori estimates need basic information on the circuit to be designed, on the architecture in which it is to be designed, and on the layout process that performs the implementation of the circuit into the architecture [3, 4]. In this position statement, we consider the circuit information. Apart from the number of gates (or blocks) in the circuit, its number of inand outputs, its number of nets and number of pins, the most important information is the notion of interconnection complexity of the circuits netlist. The interconnection complexity information is provided by Rent’s rule [5]